Embedded memories may consume 50% or more of a die area, which is expected to increase in the coming years. New models are being generated to test algorithms or procedures on the memory units. However, traditional algorithms and procedures fall short in stressing and detecting faulty memory models. Further, flexibility may be beneficial in test procedures to assure that any algorithms or procedures meet all, or most, encountered faults. Generating test algorithms may present many issues, including trade-offs to manage overhead, pipelining, power, and tester runtime. Thus, there is a need for a robust failure analysis tool to assure memory yields may be raised to an acceptable level.
Generally, a memory unit will have a common set of interface pins. For example, the interface pins may include an address, data in, data out, and various types of control signals for managing the read and write operations for the memory. Additional features have been added that may perform special functions, which may include forcing an operation to take longer on a read or write access (e.g., margin test), where the internal circuitry is adjusted to determine if a failure is close or imminent. In order to force the operation to take longer, additional resistance may be added into the memory. Further, the memory may include power down modes, which may power down the peripheral circuitry, but leave the content of the memory in place. It is also beneficial to reduce the power consumption, or increase the testability of the memory. However, while memory units have been designed with a robust test suite, the available test procedures are limited, and cannot be customized by the user testing the memory.
As more and more functionality is getting integrated into system-on-chip (“Sort”) designs, there is a steady increase in the amount of memories present on the chip. Based on the International Technology Roadmap for Semiconductors (“ITRS”), it can be as high as 90% of the chip area. Moreover, the density of the memories may be highest on a semiconductor chip. Thus, to ensure that the chip is of a sufficient quality, the memory must also be determined to be a similar quality. However, with changes in semiconductor technologies, starting from MOS, moving on to CMOS, SOI, and FINFET, and with technology moving to smaller and smaller geometries, it is hard to predict what kind of defects may be present inside a memory on a chip.
Currently, when testing a memory, a designer is provided with a predefined set of testplans by the testplan designer. However, these testplans may be limited in number, and may not be sufficient to test all possible scenarios that a designer may wish to test. Further, it is currently burdensome to add new testplans based on user input, as the testplans have to be hardwired into the memory controller.
To avoid field returns, user should be able to detect and diagnose these failures. In order to achieve this goal, a small piece of hardware, memory-built-in-self-test (“MBIST”) logic may be made part of the chip. This on-chip hardware may generate a series of read and write operations, also known as algorithms, to test the memories. These algorithms need to be written in a design language (e.g., a hardware design language), which may need an underlying hardware implementation of this grammar. Since user needs to design their own algorithms for testing purposes, the simpler the grammar, the better it is for the user to adopt and write new algorithms with minimum dependency on the vendor providing the MBIST solution. At the same time, it may be implemented with less hardware as it may reduce the area overhead.
Thus, it may be beneficial to provide an exemplary extended test support feature, which may be used in conjunction with the various features that may be incorporated into a memory.